1. Field of the Invention
The present invention generally relates to a tester for evaluating influence given to a terminal unit by variations in propagation delay time of information cells transmitted through a high-speed wide-band ISDN (Integrated Services Digital Network) system, and more particularly to an ATM cell delaying circuit for giving variable delays to the ATM cells.
The ATM (Asynchronous Transfer Mode) transmission technique is considered a promising means in implementing a transmission network of the high-speed wide-band ISDN system. With the ATM transmission, a variety of information or data are divided into blocks known as cells in the art, each of which has a fixed length and is affixed with a header, wherein transmission efficiency is improved through statistical multiplexing of these cells. Consequently, the propagation delay time of the cells on the network tends to vary in dependence on the amount of traffic. (H. Murakami et al., Considerations on ATM Network Performance Planning, IEICE Trans. Commun., Vol. E75-B, No. 7, July, 1992, hereby incorporated by reference.) Accordingly, means for correcting the variation in the propagating delay time must be incorporated in the terminal unit of the high-speed wide-band ISDN system. (H. Uematsu et al., STM Signal Transfer Technique in ATM Network, Conference Proceedings of IEEE International Conference on Communications, Jun. 14-18, 1992, Chicago, Ill., hereby incorporated by reference.) The nature of the ATM network with respect to such variation in delay must be known. Such nature of variation can be evaluated according to the present invention by generating a cell stream which is formed by adding a given delay to a cell stream which has no variation in delay, which is then passed through the ATM 1network for evaluation.
2. Description of the Prior Art
FIGS. 2A and 2B of the accompanying drawings show schematically structures of an ATM cell delay circuit known heretofore. In the case of the circuit configuration shown in FIG. 2A, a delay adding circuit 4 applies a desired amount of delay to an input signal. The delay adding circuit 4 is constituted by a multi-stage shift register. In general, in the ATM network, the transmission rate is selected high (e.g. 155,52M bps or more) with a view to enhancing the statistical multiplexing effect. Consequently, a shift register of a large capacity is required in order to increase the delay time to be added or applied to the input signal. Moreover, with the circuit configuration shown in FIG. 2A, it is difficult to accommodate change or vibration in the propagation delay time which is a feature characteristic of the ATM network.
FIG. 2B shows another example of the ATM cell delay circuit known heretofore. This circuit differs from that shown in FIG. 2A in that a cell filter 2 is additionally provided for extracting only the cells to which the delay is to be applied. With the arrangement shown in FIG. 2B, the delay time to be added can significantly be increased, while allowing variations in the propagation delay time. However, since the propagation delay time is closely related to cell arrival time interval, difficulty is involved in controlling the width of distribution or dispersion of the delay times.
Next, operation of the ATM delay cell delay circuits shown in FIGS. 2A and 2B will be described by reference to FIGS. 3A and 3B, in which FIG. 3A is a timing chart for illustrating a distribution of arrival times of those cells which are extracted from the input signal to be delayed, and FIG. 3B is a timing chart for illustrating operation of the delay adding circuit 4 constituted by the shift register having a number of stages corresponding to, for example, five cells. An input signal "1" shown in FIG. 3A can make appearance at the output of the shift register only after five cells have been inputted to the delay adding circuit 4 in succession to the input signal "1". Consequently, the delay times as added to the cells vary in dependence on the dispersion of the cell arrival times. In the case of the abovementioned example, the input cells are delayed by 5.times.Pa on an average, wherein Pa represents a mean cell arrival time interval of the input signal. When there is included a quiescent period in the communication, the quiescent period h in the output signal will be covered at least partially by the delay time as added.
In a two-way communication in which an answer is returned to an query message, communication is performed in such manners as illustrated in FIGS. 3A and 3C when the delay adding circuit shown in FIG. 2B is employed. Assuming that the cells shown at f in FIG. 3B represent information at the start of the communication, the two-way communication is so performed that only after the answer signal i shown in FIG. 3C is sent back in response to the information d shown in FIG. 3A, the succeeding information e shown in FIG. 3 is sent out. Consequently, when a delay is added to the communication, the information of the cells "6" to "10" contained in the input signal d shown in FIG. 4 can not be outputted until the input signal i is sent back when the delay adding circuit 4 operates in the manner illustrated in FIG. 3A. However, because the information of the cells "6" to "10" is not transmitted, the answer signal i is not sent back, resulting in that the input signal e is not sent out, whereupon the communication is terminated at this time point, giving rise to a serious problem.
The circuit configuration shown in FIG. 2A requires large scale hardware for applying a great amount of delay. Moreover, the delay time has to be maintained at a constant value. With the circuit configuration shown in FIG. 2B, the amount of hardware as required can be reduced with the amount of delay to be added being variable. However, because of strong correlation observed between the permissible amount of delay and the cell arrival time interval, the delay to be added will remain at a constant value when the arrival time interval between the input cells is constant, which means that the circuit configuration shown in FIG. 2B is not suited for the ATM cell delaying application in the two-way communication.